Phase-looked loop is a vitally important device. Phase-looked loop is analog and mixed signal building block used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing, clock recovery, and synchronization.
Prior Art FIG. 1 illustrates a block diagram of a basic architecture of two types of conventional phase-locked loops, which are a conventional phase-locked loop 110 and a conventional fast-locking phase-locked loop 120. The conventional phase-locked loop 110 typically consists of a phase-frequency detector (or phase detector), a charge-pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider in a loop. However, to understand phase-locked loops fundamentally, phase-locked loops without any frequency divider in a loop will be considered here. The phase-frequency detector (or phase detector) is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or phase detector). Therefore, change in the low-pass filter's output voltage is used to drive the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.
In the conventional phase-locked loop 110 of Prior Art FIG. 1, lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the difference between the input signal frequency and the initial voltage-controlled oscillator's frequency as follows:
            (                        ω          in                -                  ω          osc                    )        2        ω    0    3  where ωin is the input signal frequency, ωosc is the initial voltage-controlled oscillator's frequency, and ω0 is the loop bandwidth. The loop bandwidth must be wide enough to obtain a fast lock-in time. But the loop bandwidth is also constrained by the input signal frequency. Most systems require a fast lock-in time without regard to the input signal frequency, bandwidth, and output phase jitter due to external noise. However, the conventional phase-locked loop 110 shown in Prior Art FIG. 1 has suffered from slow locking. Thus, time and power are unnecessarily consumed until the phase-locked loops are in lock. In addition, the conventional phase-locked loop 110 has taken a vast amount of time to be simulated and verified before they are fabricated since the simulation time of phase-locked loop circuits is absolutely proportional to time that is required the phase-locked loops to lock. This long simulation adds additional cost and serious bottleneck to better design time to market. In addition, the conventional phase-locked loop 110 has also suffered from harmonic locking. Especially harmonic locking is that the phase-locked loop locks to harmonics of the input signal when a multiplier is used for the phase detector. For these reasons, the conventional phase-locked loop 110 of Prior Art FIG. 1 is very inefficient to implement in an integrated circuit or system-on-chip (SOC).
To overcome the drawbacks of the conventional phase-locked loop 110 of Prior Art FIG. 1, a conventional fast-locking phase-locked loop 120 of Prior Art FIG. 1 is illustrated. The conventional fast-locking phase-locked loop 120 consists of a digital phase-frequency detector, a proportional-integral controller 122, a 10-bit digital-to-analog converter 124, and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop is costly, complicated, and inefficient to implement in system-on-chip (SOC) or integrated circuit (IC) because additional blocks such as the proportional-integral controller 122 and the 10-bit digital-to-analog converter 124 take much more chip area and consume much more power. Since there are much more functional blocks integrated on the same chip, the chip area of the conventional fast-locking phase-locked loop 120 is about three times as large as that of the conventional phase-locked loop 110. At the same time, complicated additional functional blocks in a loop make the stability analysis very difficult. The complexity increases the number of blocks that need to be designed and verified. This long design and verification adds additional cost and serious bottleneck to better design time to market, too. The conventional fast-locking phase-locked loop 120 might improve the lock-in time, but definitely results in bad time-to-market, higher cost, larger chip area, much more power consumption, and longer design time.
Thus, what is desperately needed is a cost-effective fast-locking phase-locked loop that can be highly efficiently implemented with a drastic improvement in a very fast lock-in time, lock-in time controllability, performance, cost, chip area, power consumption, stand-by time, and fast design time for much better time-to-market. At the same time, serious harmonic locking problems have to be resolved. The present invention satisfies these needs by providing variable lock-in circuits.